Currently, deep sub-micron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reducing the size of CMOS transistors and increasing transistors density on integrated circuits (ICs) has been a principle focus of the micro electronics industry.
A ULSI circuit can include CMOS field effect transistors (FETs) which have semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and the source regions generally include thin extensions (shallow source and drain extensions) that are disposed partially underneath the gate to enhance transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both n-channel and p-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region just below the top surface of the substrate to form the source and drain extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, sidewall spacers, which abut the lateral sides of the gate structure, are provided over the source and drain extensions. With the sidewall spacers in place, the substrate is doped a second time to form deep source and drain regions. During formation of the deep source and drain regions, further doping of the source and drain extensions is inhibited due to the blocking capability of the sidewall spacers.
As the size of transistors disposed on ICs decreases, transistors having shallow and ultra-shallow source/drain extensions become more difficult to manufacture. For example, a transistor may require ultra-shallow source and drain extensions with a junction depth of less than 30 nanometers (nm). Forming source and drain extensions with junctions depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation techniques, for example, have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extensions vertically downward into the bulk semiconductor substrate. Also, conventional ion implantation and diffusion dopant techniques make transistors on the IC susceptible to short-channel effects, which result in a dopant profile tail distribution that extends deep into the substrate.
To overcome some of these concerns, the source and drain regions can be raised by selective silicon epitaxial growth (SEG) to make connections to source and drain contacts less difficult. The raised source and drain regions provide additional material for contact silicidation processes and reduce deep source/drain junction resistance and source/drain series resistance.
One of the considerations in creating raised source and drains is the separation distance provided between the raised source and drains and the polysilicon gate. Another concern is the protection of the sidewalls of the polysilicon gate during the selective epitaxial growth of silicon. If the polysilicon gate sidewalls are exposed during selective epitaxial growth, unwanted growth will occur at the exposed areas of the polysilicon. It is possible to use a conventional self-aligned to encapsulate the polysilicon and protect it during the selective epitaxial growth of silicon during the creation of the raised source and drains. However, in practice, it is difficult to create the spacers with precise distances and ensure protection of the polysilicon gate sidewalls, since it is difficult to prevent exposure of the polysilicon during the etching process.